1. Field of the Invention
The present invention generally relates to techniques for verifying the correctness of a circuit design. More specifically, the present invention relates to an input vector generation technique for achieving coverage closure which biases random input stimuli based on a temporal coverage property.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in the number of transistors per semiconductor device. This increase in transistor count is empowering computer architects to create digital circuit designs with an ever-increasing design complexity. Consequently, as digital circuit designs become more complex, the effort required to verify the correctness of their implementation also becomes more involved.
To verify the functionality of a circuit design, circuit design verification teams typically apply random input stimuli onto a circuit design under verification (DUV) to stimulate the DUV and compare the response from simulation to the expected response. Simulating the DUV against random input stimuli is a stochastic process which relies on a high volume of input vectors to achieve a reasonable coverage of the behavior of the DUV. However, as the circuit designs become more complex, the random input stimuli become less effective at covering the important corner cases of the DUV.
Circuit design verification teams have attempted to guide the test selection process to effectively cover the important corner cases of the DUV. In doing so, they have attempted to employ methods which include using directives from the designer, non-covered bins in SystemVerilog covergroups as supplementary constraints, genetic algorithms, user-supplied additional constraints, and Bayesian networks or Markov chains. Unfortunately, none of these approaches provides a complete and automatic solution for biasing the random input stimuli toward achieving coverage closure.
Hence what is needed is a more effective technique for guiding input stimuli toward the important cases of a circuit design under verification.